ELogs/Electronics
< ELogs
Electronic Log for Electronics Development
Oxford
Power supply board
Ready for experimental visit to Trento, 28th September 2025
- Power distribution board required for QuARC.
- Provide power for Raspberry Pi and DDC boards from single DC input:
- 5V/5A for Raspberry Pi via USB-C
- >7.5V (5A?) for DDC board daisy chain via 2.5mm barrel
- Single USB-C PD input: 20V/5A
- Needs USB-C PD voltage negotiation chip
- Fallback option with 20V DC 2.5mm barrel jack input
- LEDs to indicate each voltage is provided correctly:
- 20V input
- 5V to Raspberry Pi
- >7.5V to DDC boards
- Should be able to switch off LEDs
- Necessary to switch between input power supplies?
- Ensure both power outputs stable: no drop-outs!
- Potential for USB-C PD to drop out when voltage renegotiated?
DDC Photodiode Board Rev.F
Upon completion of power distribution board
- Remove RESET connection from CC2 pin on all DDC board USB-C connections
- Resize DDC board to accept Hamamatsu S12362 16-element photodiode array in place of Hamamatsu S12915-16R single photodiodes
- Reduces pitch from 3mm to 2.5mm
- 2 photodiode arrays per DDC board (2 x 16 element arrays = 32 channels)
Scintillating Fibre Profile Monitor Front-end Boards
Upon completion of Rev.F board
- Integration of scintillating fibre profile monitor based on design from Blake Leverington, University of Heidelberg
- Hamamatsu S17285 photodiode arrays to couple to scintillating fibres
- Interface board needed between USB-C connection from FPGA and photodiode arrays
- Acquire data; distribute timing signals
Imperial
QuADProBe FPGA Upgrade
- QuADProBe QAD to be upgraded from USB104+Raspberry Pi to Kria:
- Kria available off-the-shelf but carrier board needed
- Imperial to design carrier board with multiple I/O for QuADProBe:
IO specification
- Connections for AMD Kria K26 system-on-module
- 11 “USB-C” IO connector
- Vertical right-angle (“flag”) connector
- 5x differential-pairs, at-least one connected to HP clock-capable pins
- 4x single-ended, to 3v3 HD pins
- 20V power - power-enable, O/V and O/C protection
- 1 “USB-C” IO connector
- Vertical right-angle (“flag”) connector
- 3x differential-pairs, connected to HP global-clock pins
- 4x single-ended, to 3v3 HD pins
- 20V power - power-enable, O/V and O/C protection
- GbE via RJ45
- M.2 SATA disk
- Or NVMe disk? IIRC can be made resistor-changeable to PCIe?
- M.2 PCIe?
- A+E key? M key?
- 2 lane PCIe
- uSD card
- RPI5-compatable PCIe
- 16-pin, single-sided, 0.5mm pitch FFC
- Connect to PL GTH transceivers
- 4-pin fan-header?
Power specification
- USB-C power connection – 5A @ 20V
- Requires negotiation
- Barrel-jack fall-back power
- Hold-up caps?
Mechanical specification
- As low-profile as possible
- Not overly constrained in lateral dimensions – as compact as reasonably possible
- Mounting holes
- Heatsink?
- All connector on one edge?
- Except RPI PCIe (and fan-header if used)
To-do
- Swap USBs to flag-type
- Make power switches disabled by default (pull-up on En# lines)
- I2C for power negotiator
- 20V USB-C PD/DC power input
- 11 x USB-C sockets connected to PL for detector interface