From mp@hep.ucl.ac.uk Mon Jan 19 19:57:25 1998 Date: Mon, 19 Jan 1998 14:55:33 GMT From: "MARTIN POSTRANECKY,UCL-PHYSICS DEP,HEPP GROUP,GOWER ST,LONDON WC1E 6BT,TEL:(00-44)-[0]171-419 3453,FAX:[0]171-380 7145" To: meh@ax8.hep.ucl.ac.uk, mp@ax8.hep.ucl.ac.uk Pipeline registers and addresses ================================ This example shows the relationship of the pipeline registers and addresses. The input signals are from the GFLT to the MTC. The output signals are from the LTC to the backplane. The effects of time delays in the system are hidden in the Jumpback value which also determines the position of time-zero in the window. Inputs : from GFLT ------------------ ----------------------------------------------------------------- GBCN | 219 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | ----------------------------------------------------------------- _______ BCN0 _______| |_______________________________________________ _______________________________ Accept GBCN=3 _______________________________| Outputs : from LTC ------------------ End Copy Pipeline End (=Size) Trigger Address Address | | | ----------V-----------------------V-----------------------V------ Pipeline Addr |437|438|439| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |439| 0 | 1 | 2 | 12| ----------------------------------------------------------------- <-- Jumpback=6 --------> <-- Window=4 --> ___ ___ ___ ___ ___ ___ ___ ___ NOTCLK2 | |___| |___| |___| |___| |___| |___| |___| |___| _______________________________________ ___ NOTTRANSFER |___________________| Window End (=Size) | ----------------------------------------------------------V------ Window Addr | 7F | 7F| 0 | 1 | 2 | 3 | 7F| ----------------------------------------------------------------- ----------------------------------------------------------------- Buffer Addr | F | F | Buffer Count | F | ----------------------------------------------------------------- <------------- pipelining --------------> <- transfering -> data data Registers : ----------- Pipeline ----------------------------------------------------------------- Count |437|438|439| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10| 11| 12| register ----------------------------------------------------------------- (= Fast Clock) Notes ----- 1. The values of the pipeline registers in this example are : Pipeline End (=Size) = 439 ( = pipeline length - 1 ) MINUS Jumpback = 434 ( = Pipeline End (=Size) + 1 - Jumpback ) Window End (=Size) = 3 ( = window length - 1 ) Trigger Address = 5 ( = 2 * GBCN - 1 : always odd under GFLT Control) End Copy Address = 2 ( = Trigger Address - Jumpback + Window End (=Size) ) Trigger Address and End Copy Address are set after they occur. The other three registers are set up in the Stand By state. 2. The phase between the 96ns clock and the LSB of Pipeline Address is affected by the following two registers (the others have no effect) : Pipeline End (=Size) must be 439 under GFLT Control, and odd under ROC Control. Under GFLT / MTC Control every BCN0 zeros the pipeline address. For even values of Jumpback the phase changes during Transfer, with odd values it does not change. The usual 48ns Transfer rate is assumed throughout this example. 3. Under ROC Control the Trigger Address can be odd or even. 4. Pipeline Address is the backplane signals RA0 - RA9. The DPM Address bus on the backplane is made up of two parts : Window Address is DA0 - DA6 (the 7 LSBs), Buffer Address is DA7 - DA10 (the 4 MSBs). 5. The address after the Transfer line changes allows the front-end cards one Transfer clock period to change their memory write enables. Data may be copied to DPM Address 7FF and may be corrupt (this is OK). 6. Pipeline Address is not available in a register but the Pipeline Count ( = Fast Clock ) register is included in the example for completeness. 7. Normally the MTC and all LTCs should have the same register values but other configurations are possible. JBL - UCL : 31 Jul. 1992 12 Jul. 1992