From mp@hep.ucl.ac.uk Wed Jan 28 12:14:00 1998
Date: Wed, 28 Jan 1998 11:07:42 GMT
From: "MARTIN POSTRANECKY,UCL-PHYSICS DEP,HEPP GROUP,GOWER ST,LONDON WC1E
     6BT,TEL:(00-44)-[0]171-419 3453,FAX:[0]171-380 7145" <mp@hep.ucl.ac.uk>
To: meh@ax8.hep.ucl.ac.uk, mp@ax8.hep.ucl.ac.uk
Subject: LCC_CHECKS-2.TXT;1


From:	VXDESY::CARTER       10-MAY-1994 
========================================


  Notes on Testing the Calibration Controller
  -------------------------------------------
   The controller uses a page system to comunicate with the memory and
  various registers which need to be set up before the control word is
  sent to the driver.  The page register resides at address '0' and the
  data sent to this address is latched and should point to the required
  register or memory field.

  1) To check the memory.
     Write 0 to address 0, then write a recognisable pattern to addresses 2
     through 20, or for the full memory bank for a more definitive test.
     Read this back and look for errors.
     Write 1 to address 0, then check as above.
     Write 2 and check, then 3 and check. This covers the 4 memory fields.

  2) To check the Beam Crossing Counter.
     Write 9 to address 0, then write a 4 digit no. to address 2. Read this
     back and check for errors.
 
  3) To check the Fine Timing Register.
     Write A to address 0, then write a 2 digit number to address 2. Read
     this back and check for errors. Ignore the 6 Fs in front of the number.
  
  4) To check the Sequence Restart Pointer.
     Write B to address 0, then a 4 digit no. to address 2. Read this back
     and check for errors. 

  5) To check the Control and Status Register.
     Write 8 to address 0, then 1 to address 2. Check the LCC ready led is
     out. Write 42 to address 2, check this led is lit. Write 2 to address 2
     and if the 10Mhz clock is active the LCC ready led should go out. The
     oscillator should be providing trigger pulses at this time. (-ve TTL)

  6) To check the Sequence Restart system is working, write B to address 0.
     Read the data at address 4. This should equal or be less than the number
     written in 4) above. Reading this data at random should give differing
     values which never exceed the value written in 4) above, providing that
     the self triggering system is enabled
    
     NB: The trigger pulse automatically produces a 'latch' pulse which
     --- latches the memory o/p into the driver. The following trigger produces
         a driver o/p based on that data, then latches data into the driver for 
         the next trigger.

   To set memory for a type 1 trigger crate.
   ------------------------------------------
  1) Write 0 to add. 0, then 4410 to add. 2 and FFFF8880 to add. 4
  2) Write 1 to add. 0, then 4444 to add. 2 and FFFF8888 to add. 4
  3) Write 2 to add. 0, then   44 to add. 2,and      208 to add. 4
  4) Write 3 to add. 0, then  BFF to add. 2,and      FFF to add. 4

     Providing the self trigger system is running ( by writing 2 to the
     control and status register), and the sequence restart pointer is at 2
     Select End should alternate high and low at every trigger pulse. (Z LTCCs 
     only)