From mp@hep.ucl.ac.uk Wed Jan 28 12:11:02 1998
Date: Wed, 28 Jan 1998 11:07:02 GMT
From: "MARTIN POSTRANECKY,UCL-PHYSICS DEP,HEPP GROUP,GOWER ST,LONDON WC1E
     6BT,TEL:(00-44)-[0]171-419 3453,FAX:[0]171-380 7145" <mp@hep.ucl.ac.uk>
To: meh@ax8.hep.ucl.ac.uk, mp@ax8.hep.ucl.ac.uk
Subject: LCC_CHECKS-1.TXT;1



		CAL. CONTROLLER TESTING INSTRUCTIONS 
		====================================

		Dick Carter, RAL, 22 March 1994
		-------------------------------
		( Modified by MP - UCL,	23 March 1994
					 7 July 1994
					12 August 1994
					 3 May 1995

1a)	A delay chip DL1 ( 20A20112 ) has links 1 - 9 coupled to it.
	Link LK1, giving the shortest delay, should be shorted.
	This sets the timing for CAL NOW.			( Diag.21)

1b)	Under DL2 delay line, short pins 7 & 11 together by placing
	a thin wire inside holes of the DIL sockets under the IC.
								( Diag.21 )

2)	There is a further link, LK10 which must be connected.
	Pins 1 and 2 should be shorted.				( Diag.21 )

3)	Using the 16 bit backplane option on ROCTEST write 0 at address 0.
  	Next change the address to something like 2 - 20, and write something
	distinctive like 1234 and see if you can read it back. 
	Repeat this by writing 1 at address 0, then 2 then 3. 
	This tests the 4 memory fields.
	Leave field 4, ie 3 at address 0, with FFF in address 2, and BFF in
	address 4. 
	This ensures that the cal now enable bit is set high,and the
	and the SEL END bit alternates when testing the trigger system.

4)	Write A at address 0, then write a 2 bit number to address 2, 
	and read it back. 
	If OK write 2 to address 2, and leave it in. 
	This is the sequence restart register which means the memory address 
	will reset every second trigger.

5)	Write B to address 0, then write a 2 bit number to address 2 
	and read it back. 
	This is the beam crossing counter.

6)	Still with B at address 0, write a 2 bit number to address 4,
	and read it back. 
	This is the fine timing chip used in conjunction with the beam
	crossing counter.

7)	Write 8 at address 0. 
	Write 0 at address 2 and then a 2. 
	With a scope find out if trigger pulses appear at the 
	Fischer plug  J.4 = "TEST TRIGGER OUT" .		( Diag.20 )
	They will be TTL at around 10 Hz, the frequency is not important.
	Still at address 2, write 62. 
	The "LCC READY" LED should light. 
	If so, write 1 and the LED should go out.
	Next write a 2 again and check you still have trigger pulses. 
	If so, write 9 to address 0, then read data at address 2. 
	If the sequence restart reg. was set at 2, this reading should 
	be a 1 or a 2, and if you keep reading, it should changed occasionally
	from 1 to 2 or vice-versa. 
	This is the address counter and should go up to whatever you have put 
	in the sequence restart reg.




									/cont.



					- 2 -



8)	Provided you have trigger pulses and have put BFF and FFF in 
	addresses 2 and 4 ( doesn't matter which is in which) 
	of field 4 memory, 					( Diag.21 )
	you should find the CAL NOW pulse at pin A 29 at the backplane. 
	( If it's not there you could try at the timing link and follow it 
	through )
	Assuming all is well look at pin A 28 backplane.	( Diag.21 )
	This is the SEL END signal, and should alternate high and low at 
	the trigger frequency. 
	This signal tells the Z board which end of the chamber the pulses 
	originate. 
	( If it's not there you could look at pin 17 on the field 4 ram )