ELogs/SoniaEscribano: Difference between revisions
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We have two different types of boards (revB and revC) that differ in the number of PD and the space between them. They are directly coupled to the PD, and need a power cable and a PMOD connection that goes to the FPGA. | We have two different types of boards (revB and revC) that differ in the number of PD and the space between them. They are directly coupled to the PD, and need a power cable and a PMOD connection that goes to the FPGA. | ||
* revB: 16 photodiodes, spaced 2.86 mm. Uses 12V power cable. | * revB: 16 photodiodes, spaced 2.86 mm. Uses 12V power cable. | ||
* revC: 32 photodiodes, spaced 3.0 mm. Uses 7V power cable -> revD is a modification of revC, with a change in the heat | * revC: 32 photodiodes, spaced 3.0 mm. Uses 7V power cable -> revD is a modification of revC, with a change in the heat management. | ||
'''4. FPGA''' | |||
The FPGA is used to read the boards and transfer the data to the PC. The FPGA automatically loads the last code designed, but if not we can load it with Vivado: the code used is FTDI.h, which uses libFTDI libraries so they need to be installed in the laptop. We have 2 different boards: | |||
* Nexys board: | |||
* usb104: powered via USB and connected to the board with a PMOD cable. | |||
If we want to run the DAQ, first we have to compile the code as follows: | |||
MacBook: g++ -L/opt/local/lib -I/opt/local/include/libftdi1 -lftdi1 -std=c++17 -O3 FTDI.cpp -o FTDI | |||
Nuc PC: g++ -L/usr/lib64 -I/usr/include/libftdi1 -lftdi1 -std=c++17 -O3 FTDI.cpp -o FTDI | |||
We can then run the code with the adequate parameters: | |||
./FTDI nexys/usb104 num_DDCports FSR t_INT(us) nmeasurements outputfile board (testmode) | |||
We can also visualise "live" (reads from average.csv) using the livePlot code. | |||
g++ -o livePlot livePlot.cpp `root-config --cflags --glibs` -O3 | |||
./livePlot num_DDCboards FSR yScale revB/C reversetrue/false (clean folder background.txt backST.txt frontST.txt ...) | |||
'''5. Data acquisition''' | |||
Running FTDI code the average time per read should be ~170us, giving a data transfer speed of ~0.47MB/s. | |||
* We acquire data using FTDI.cpp code, changing the output file to Run001.txt, Run002.txt and so on. | |||
* If we want to acquire data and show it live we need to use progh.sh | |||
./prog.sh nexys/usb104 4 350 0 170 100000 50 true capture.txt revB/C true/false (fit/test/clean) (folder background.txt backST.txt frontST.txt ...) | |||
'''6. Data analysis''' | |||
'''Questions''' | |||
* Boards: What needs to be done to them? Vivado codes into FPGA but boards? Daisy chaining? What was done in terms of usbC connection? | |||
* FPGA: no longer using nexys? What issues did we have with both of them? | |||
* Experiment: just use FTDI code changing the run number? where are these runs saved? Possible errors during data acquisition? test mode? | |||
* Data analysis: parameters for fit based on what? | |||
== GUI == | == GUI == |
Revision as of 10:46, 25 September 2023
Electronic Log for Sonia Escribano
To Do
- Port Saad's FPGA data replay code to Python → copied
- Duplicate functionality of Fern's GUI in D3.
Knowledge Transfer
1. Scintillators
The main properties of our scintillators are:
- ρ = (1.03±0.01)g cm-3
- decay constant = 2.5 ns
- maximum emission at 425 nm (blue-violet)
- light output = 56% of anthracene
- n = 1.57
In total we have 302 scintillator sheets. Their production mechanisms and average thicknesses are summarised in this file []. The order in which the scintillators are assembled in each stack is available in the GUI, inside every experimental run log.
- Each sheet thickness is measured in 8 different points of the scintillator: 4 corners, and 4 middle parts of each side.
- The uncertainty is simply calculated as the standard deviation.
- For the scintillator stacks used in Manchester and PARTREC we measured the thickness in 3 points.
- Clear polished scintillators (machine block) offer the best light output.
2. Photodiodes
The first prototype of the QuARC had a CMOS sensor, but it was then upgraded to photodiodes coupled to each sheet individually. There is a direct coupling, so no optical gel is used.
- Model = hamamatsu S12915-16R
- Effective photosensitive area = 6.0 mm2
- Spectral response wavelength between 340-1100 nm
- Quantum efficiency peaks at 960 nm
3. Boards: DDC232
We have two different types of boards (revB and revC) that differ in the number of PD and the space between them. They are directly coupled to the PD, and need a power cable and a PMOD connection that goes to the FPGA.
- revB: 16 photodiodes, spaced 2.86 mm. Uses 12V power cable.
- revC: 32 photodiodes, spaced 3.0 mm. Uses 7V power cable -> revD is a modification of revC, with a change in the heat management.
4. FPGA
The FPGA is used to read the boards and transfer the data to the PC. The FPGA automatically loads the last code designed, but if not we can load it with Vivado: the code used is FTDI.h, which uses libFTDI libraries so they need to be installed in the laptop. We have 2 different boards:
- Nexys board:
- usb104: powered via USB and connected to the board with a PMOD cable.
If we want to run the DAQ, first we have to compile the code as follows:
MacBook: g++ -L/opt/local/lib -I/opt/local/include/libftdi1 -lftdi1 -std=c++17 -O3 FTDI.cpp -o FTDI Nuc PC: g++ -L/usr/lib64 -I/usr/include/libftdi1 -lftdi1 -std=c++17 -O3 FTDI.cpp -o FTDI
We can then run the code with the adequate parameters:
./FTDI nexys/usb104 num_DDCports FSR t_INT(us) nmeasurements outputfile board (testmode)
We can also visualise "live" (reads from average.csv) using the livePlot code.
g++ -o livePlot livePlot.cpp `root-config --cflags --glibs` -O3
./livePlot num_DDCboards FSR yScale revB/C reversetrue/false (clean folder background.txt backST.txt frontST.txt ...)
5. Data acquisition
Running FTDI code the average time per read should be ~170us, giving a data transfer speed of ~0.47MB/s.
- We acquire data using FTDI.cpp code, changing the output file to Run001.txt, Run002.txt and so on.
- If we want to acquire data and show it live we need to use progh.sh
./prog.sh nexys/usb104 4 350 0 170 100000 50 true capture.txt revB/C true/false (fit/test/clean) (folder background.txt backST.txt frontST.txt ...)
6. Data analysis
Questions
- Boards: What needs to be done to them? Vivado codes into FPGA but boards? Daisy chaining? What was done in terms of usbC connection?
- FPGA: no longer using nexys? What issues did we have with both of them?
- Experiment: just use FTDI code changing the run number? where are these runs saved? Possible errors during data acquisition? test mode?
- Data analysis: parameters for fit based on what?
GUI
- Modify code to give - instead of 0 when fit not performed ✓
- Plot data with 20 points ✓
- Upload files to new directory
- Modify position of error bars ✓
- x-axis zooming problem: only some numbers work ✓
- Fix misalignment between PDdata and FITdata ✓
- Test access from NUC PC
Replay + Fit
- Check parameter limits with Saad
- Fit data with 20 points instead of 10 to avoid harsh lines ✓
- Print date and time of original file, not produced ones ✓
- Create only one calibration with backST and frontST
- Test code on NUC PC
- Add fitted rate to header ✓
Done
- PARTREC pictures uploaded to: /unix/pbt/data/partrec/20221125/Pictures
- Cut Mylar foil sheets for Manchester experiment
- Talk to Derek about Mylar foil.
- Probation meeting with Simon (fill form)
- Set up new MacBook Pro: might need dual booting (talk to Tony Hoare about Windows).
- Set up Geant4 simulations of detector → copied and running
Quick-start
- Get user name + email ✓
- Get ID card: book appointment online ✓
- Mandatory safety training courses: Safety Induction + Fire Safety ✓
- Book departamental safety induction with Lee Bebbington ✓
- Mandatory training courses: GDPR, information security, freedom of information, DSE, diversity, unconscious bias, ✓
- Create a wiki account ✓
- Register for an account on the HEP Linux cluster (email support@hep.ucl.ac.uk) ✓
- Install Geant4 (instructions: [1]) ✓
- Set up bank details online on myHR ✓
Important Dates
Date | Event |
---|---|
23rd Sep 2022 | VIVA York |
20th Oct 2022 | Prague |
21st Oct 2022 | HEP Seminar |
25-26th Oct 2022 | Manchester beam test |
24-25th Nov 2022 | Groningen beam test |
30th Nov - 2nd Dec 2022 | FRPT Conference Barcelona |
20th Jan 2023 | PhD Graduation York |
8th Feb 2023 | QuARC Seminar @Bristol |
5th Apr 2023 | PGI Seminar @Queen Mary |
18th May 2023 | Clatterbridge beam test |
10th-16th June 2023 | PTCOG Conference Madrid |
3rd-7th July 2023 | HIT Online course |
25th-28th July 2023 | FPGA Course RAL |