Proton Calorimetry/Equipment/FPGAs DDC232

Useful Material

Technical Documents

• DDC232 datasheet.
• Zybo Z7 manual.

Presentations

• I/O signals and operation of TI DDC232CK based on datasheet information. Slides available here.
• Results of simulation of FPGA design discussed here.
• UART interface between FPGA and PC discussed in this presentation.
• First operational tests discussed in this presentation.
• DDC232 design features and demo given in this presentation.

DDC232

A Texas Instruments (Dallas, Texas, United States) DDC232CK (DDC) was chosen as the current-input analogue-to-digital converter for its speed, large dynamic range and low power requirements. It is capable of measuring the currents of up to 32 photodiodes with an adjustable integration time (160μs–1s) and full-scale range (FSR, 12pC–350pC). Each of the 32 inputs on the DDC has two integrators, allowing for zero-deadtime measurements: while one integrator digitises and transfers data, the other measures the input current. The DDC is housed on a compact custom circuit board manufactured by CosyLab (Ljubljana, Slovenia), where the charge collected by a photodiode is split across two DDC inputs to give 16 photodiodes per DDC. The role of each digital signal is described below:

• CLK (input): 10 MHz clocking signal that is used to time the internal operations of the DDC, including generation of DVALID.
• CONV (input): signal that controls integration, the time period of which is equal to the integration time. When this signal toggles, the integrator of each input switches.
• DIN_CFG (input): serial data stream of the 12-bit sequence used to set key parameters of the DDC, namely the FSR and measurement precision (16-bit or 20-bit).
• CLK_CFG (input): 20 MHz clocking signal used to time sending and reading of DIN_CFG.
• RESET (input): Asynchronous active-low reset signal for the DDC to revert it to its power-up state.
• DCLK (input): 20 MHz clocking signal used to time sending and reading of DOUT.
• DVALID (output): active-low signal used to indicate that data is ready to be read on DOUT.
• DOUT (output): serial data stream of the 640-bit sequence (when in 20-bit precision mode) containing measurements of the 32 inputs.
• DIN (input): serial data input to the DDC used to daisy-chain other DDCs.

Zybo Z7-10

The FPGA used to communicate with the DDC is a Xilinx (San Jose, California, United States) Zynq- 7000 on a Digilent (Pullman, Washington, United States) Zybo Z7-10 development board, which features a built-in ARM Cortex-A9 processor and a host of peripheral connections. The FPGA design was written in VHDL using Xilinx Vivado Design Suite 2020. Further details of the design-assigned purpose of the on-board buttons, switches and LEDs are provided below:

• Clocking Wizard Status LED: the 125 MHz FPGA master clock is converted to a 120 MHz clock using the Xilinx Clocking Wizard intellectual property (IP), to allow for easier generation of the 10 and 20 MHz signals required by the DDC. This LED is on when the Clocking Wizard component of the design is generating a stable clock. All FPGA operations are timed using this clock.
• Test-mode LED: the DDC can be configured into a test diagnostic mode for debugging, in which all the inputs give a zero signal (slightly above zero due to noise and a negative current offset). This LED is on when the user has enabled the test mode, which can be toggled using the Toggle Test-Mode button and becomes active after a Global Reset press.
• State LED 1: this LED is on whenever the DDC in the power-up, idle, or configuration state.
• State LED 2: this LED is on whenever the DDC is measuring or shifting out data.
• Acquisition mode: this switch toggles between the continuous and triggered acquisition modes. In continuous mode, data will be output to the PC as fast as possible, the rate of which is dependent on the chosen integration time and the speed of the data transfer. When in triggered mode, the next measurement after the Trigger Acquisition button is pressed is sent to the PC.
• FSR Switches: these 3 switches control the 3-bit FSR code, which allows the user to choose between the 8 different dynamic ranges.
• Global Reset: this button resets all aspects of the FPGA and DDC. Any changes since the last reset in the FSR, acquisition mode or test-mode settings are applied. The DDC returns to its power-up state and reconfigures before resuming operation.
• Pause Operation: this button idles the FPGA and DDC, all signals are held at their default value apart from the 120 MHz master clock. Pressing Global Reset restarts operation.
• RGB LED: this LED will be green if the DDC is configured correctly (see section 3.1), red if configu- ration is incorrect or if too short an integration time is chosen, or blue if the first-in first-out (FIFO) interface is read when empty or is written to when full (see section 3.3).