Proton Calorimetry/Meetings/2020/06/17: Difference between revisions
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** [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/2019_Book_IntroductionToLogicCircuitsLog.pdf Introduction to Logic Circuits & Logic Designwith Verilog] | ** [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/2019_Book_IntroductionToLogicCircuitsLog.pdf Introduction to Logic Circuits & Logic Designwith Verilog] | ||
** [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/2019_Book_QuickStartGuideToVerilog.pdf Quick StartGuide to Verilog] | ** [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/2019_Book_QuickStartGuideToVerilog.pdf Quick StartGuide to Verilog] | ||
Book suggested by Killey Robert from the ELEC0028 Advanced Digital Design module | |||
** [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/David%20M.%20Harris,%20Sarah%20L.%20Harris%20-%20Digital%20Design%20and%20Computer%20Architecture,%20(2012,%20Morgan%20Kaufmann).pdf Digital Design and Computer Architecture] with [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/Harris%20D.M.,%20Harris%20S.L.%20-%20Digital%20Design%20and%20Computer%20Architecture.%20Exercise%20Solutions.pdf relative solutions] | |||
* Will finalise a first draft of her project proposal for fellowships | * Will finalise a first draft of her project proposal for fellowships | ||
Revision as of 10:14, 24 June 2020
Minutes for UCL Proton Calorimetry Meetings, 17th June (Everyone is working from home)
Present
Simon Jolly, Laurent Kelleter, Saad Shaikh, Raffaella Radogna
Raffaella Radogna
- Installed Xilinx - Vivado Design Suite on Windows
- Matt Warren generated the license key
- Provided comments for Laurent's chapter 9, chapter 2, Abstract, and Introduction.
- Started reading about FPGA programming and digital circuit
Book suggested by Killey Robert from the ELEC0028 Advanced Digital Design module
- Will finalise a first draft of her project proposal for fellowships
Saad Shaikh
- Old MacBook Pro died – now set up on DAQ laptop.
- Waiting on Ruben to respond regarding purchasing new laptop.
- Using Xilinx Clocking Wizard to generate different clock frequencies – still testing this.
- Need to finish serial UART interface example project.
- Need to convert UCF constraints file provided by TI to XDC in order to use in Vivado.