Proton Calorimetry/Meetings/2019/10/04: Difference between revisions
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# Front end (photodiode) electronics | # Front end (photodiode) electronics | ||
## replacement for AIB | ## replacement for AIB | ||
## speak to Bernard | ## speak to Bernard Bristoll (b.bristoll@ucl.ac.uk) | ||
## contact TI and to check if we can use AIB for our purposes (dedline Dec.) | ## contact TI and to check if we can use AIB for our purposes (dedline Dec.) | ||
## ask TI if we can use our customised AIB with the EVM | ## ask TI if we can use our customised AIB with the EVM |
Revision as of 11:00, 8 October 2019
Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL)
Present
Simon Jolly, Laurent Kelleter, Raffaella Radogna, Saad Shaikh
Current Status
- RR presented current status.
- Various photodiodes already purchased; DDC1128 EVM's purchased.
- Simple light injection setup with 270nm LED.
- EVM connected to photodiodes through removal of resistors on daughter board.
QuARC Task List
- Scintillator manufacture
- Photodiode coupling
- PD to single layer
- SMA connectors and plug for PD pins
- LED with optical fibres to inject light
- signal from the scope (4 channels)
- LED standalone to move the light on the stack
- “permanent" PD coupling to scintillators
- Front end (photodiode) electronics
- replacement for AIB
- speak to Bernard Bristoll (b.bristoll@ucl.ac.uk)
- contact TI and to check if we can use AIB for our purposes (dedline Dec.)
- ask TI if we can use our customised AIB with the EVM
- speak to electrical eng. for circuit board DDC232 (about 10cm stacks considering 3mm layers)
- manufacturing of 2 circuit boards: PD to SMA to board, permanent PD coupling to board
- stable coupling of PD and SMA
- mounting the circuit board in an enclosure
- Back end (FPGA/comms) electronics
- buy FPGA prototyping board
- FPGA that generates DDC232 signal (fake signal) trigger signal, each channel integrates for 200 ns, output from each channel
- test signal into the FPGA board (test fake signal from the previous point). has to behave as interfacing with the real input (trigger that says to read out and a clock that integrates each channel).
- buffer data to work at 5kHz
- COMMS to PC (interface with FPGA)
- Data analysis
- standalone version of the current analysis without ROOT
- FPGA analysis (using ROOT libraries?)
- GUI