Proton Calorimetry/Meetings/2019/10/04: Difference between revisions

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## FPGA that generates DDC232 signal (fake signal) trigger signal, each channel integrates for 200 ns, output from each channel
## FPGA that generates DDC232 signal (fake signal) trigger signal, each channel integrates for 200 ns, output from each channel
## test signal into the FPGA board (test fake signal from the previous point). has to behave as interfacing with the real input (trigger that says to read out and a clock that integrates each channel).
## test signal into the FPGA board (test fake signal from the previous point). has to behave as interfacing with the real input (trigger that says to read out and a clock that integrates each channel).
 
## buffer data to work at 5kHz
## COMMS to PC (interface with FPGA)


# Data analysis
# Data analysis
## standalone version of the current analysis without ROOT
## FPGA analysis (using ROOT libraries?)
## GUI

Revision as of 16:28, 4 October 2019

Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL)

Present

Simon Jolly, Laurent Kelleter, Raffaella Radogna, Saad Shaikh

Current Status

  • RR presented current status.
  • Various photodiodes already purchased; DDC1128 EVM's purchased.
    • Simple light injection setup with 270nm LED.
    • EVM connected to photodiodes through removal of resistors on daughter board.

QuARC Task List

  1. Scintillator manufacture
  1. Photodiode coupling
    1. PD to single layer
    2. SMA connectors and plug for PD pins
    3. LED with optical fibres to inject light
    4. signal from the scope (4 channels)
    5. LED standalone to move the light on the stack
    6. “permanent" PD coupling to scintillators
  1. Front end (photodiode) electronics
    1. replacement for AIB
    2. speak to Bernard Bristol
    3. contact TI and to check if we can use AIB for our purposes (dedline Dec.)
    4. ask TI if we can use our customised AIB with the EVM
    5. speak to electrical eng. for circuit board DDC232 (about 10cm stacks considering 3mm layers)
    6. manufacturing of 2 circuit boards: PD to SMA to board, permanent PD coupling to board
    7. stable coupling of PD and SMA
    8. mounting the circuit board in an enclosure
  1. Back end (FPGA/comms) electronics
    1. buy FPGA prototyping board
    2. FPGA that generates DDC232 signal (fake signal) trigger signal, each channel integrates for 200 ns, output from each channel
    3. test signal into the FPGA board (test fake signal from the previous point). has to behave as interfacing with the real input (trigger that says to read out and a clock that integrates each channel).
    4. buffer data to work at 5kHz
    5. COMMS to PC (interface with FPGA)
  1. Data analysis
    1. standalone version of the current analysis without ROOT
    2. FPGA analysis (using ROOT libraries?)
    3. GUI