Proton Calorimetry/Meetings/2021/11/17: Difference between revisions

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=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
*Further analysis of November test beam data, discussed in [http://www.hep.ucl.ac.uk/pbt/wikiData/presentations/2021/SS211117_UCLH_2.pptx this presentation].
*Further analysis of November test beam data, discussed in [http://www.hep.ucl.ac.uk/pbt/wikiData/presentations/2021/SS211110_UCLH.pptx this presentation].
**Compared November photodiode data to April CMOS data:
**Compared November photodiode data to April CMOS data:
***Observed consistent discrepancy in build-up to Bragg peak causing poor fits with photodiodes.
***Observed consistent discrepancy in build-up to Bragg peak causing poor fits with photodiodes.

Latest revision as of 17:40, 9 December 2021

Minutes for UCL Proton Calorimetry Meetings, 17th November

Present

Simon Jolly, Saad Shaikh, Raffaella Radogna

Saad Shaikh

  • Further analysis of November test beam data, discussed in this presentation.
    • Compared November photodiode data to April CMOS data:
      • Observed consistent discrepancy in build-up to Bragg peak causing poor fits with photodiodes.
      • WET seems to be consistent across data sets.
    • Fitting data around peak does not improve things.
    • Reverse engineered fit using fixed "correct" values of range and sigma, and varying only Birks' and phi.
      • Observe large differences in Birks' constant across data sets, photodiode fits remain worse.
  • Will perform fits with CMOS data, taking only central stripe.
    • Simon to provide WET calibration value for fitting Nikon data from November.
  • Discussed potential causes of poor fits with Laurent:
    • Could be that scintillator sheets are damaged after stripping and repainting.
    • Overarching problem of detector is non-uniform light output, dependant on beam position and light sensor position/size. Photodiodes could be missing dose.
    • Doing a test with mylar foil wrapping could be useful – especially with new sheets from Nuvia and Rev. C DDC232 boards.
  • FPGA programming:
    • Nexys Video design ready for testing with Rev. C hardware.
    • Ported PMOD design to USB104, will test and debug.
    • Will debug Matt's fix for signals crossing clock domains.
  • First draft of FRPT presentation, small changes to videos/images required.