Proton Calorimetry/Meetings/2021/01/13: Difference between revisions

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*Optimised data transfer from FPGA to PC using FTDI chip.  
*Optimised data transfer from FPGA to PC using FTDI chip.  
**Time taken to send data from FPGA to PC is negligible compared to time taken to shift data from DDC232 to FPGA.
**Time taken to send data from FPGA to PC is negligible compared to time taken to shift data from DDC232 to FPGA.
**Each board in chain adds a 0.45 MB/s requirement to data transfer speed.
**Each board in chain adds a 0.494 MB/s requirement to data transfer speed.
**Will now work on sending data from PC to FPGA over FTDI chip and C++ framework to save data to file.
**Will now work on sending data from PC to FPGA over FTDI chip and C++ framework to save data to file.
*Updating [http://www.hep.ucl.ac.uk/pbt/wiki/Proton_Calorimetry/Equipment/ZyboZ7_DDC232 equipment page on DDC232] with information on Nexys Video and new USB interface.
*Laptop has arrived and is excellent :)
*Laptop has arrived and is excellent :)
**When confident that everything on new laptop is working, will do a clean install of Big Sur on DAQ laptop.
**When confident that everything on new laptop is working, will do a clean install of Big Sur on DAQ laptop.


=== [[ELogs/FernPannell|Fern Pannell]] ===
=== [[ELogs/FernPannell|Fern Pannell]] ===
* MSci progress meeting with Jenny Thomas went very well!
**Progress meeting [http://www.hep.ucl.ac.uk/pbt/wikiData/presentations/2021/FP_ProgressInterview.pptx presentation].

Latest revision as of 16:34, 21 January 2021

Minutes for UCL Proton Calorimetry Meetings, 13th January

Present

Simon Jolly, Raffaella Radogna, Saad Shaikh, Fern Pannell

Raffaella Radogna

Saad Shaikh

  • Further investigation of daisy-chain issue in 2nd DDC232 prototype. Still unable to diagnose the problem.
    • Test mode and slowing down DCLK does not help.
    • Unclear if "copying" of data across boards is exact.
    • Added a few slides to last week's presentation.
    • Will attempt shuffling board order to see if that helps.
    • Will organise meeting with Marko.
  • Optimised data transfer from FPGA to PC using FTDI chip.
    • Time taken to send data from FPGA to PC is negligible compared to time taken to shift data from DDC232 to FPGA.
    • Each board in chain adds a 0.494 MB/s requirement to data transfer speed.
    • Will now work on sending data from PC to FPGA over FTDI chip and C++ framework to save data to file.
  • Updating equipment page on DDC232 with information on Nexys Video and new USB interface.
  • Laptop has arrived and is excellent :)
    • When confident that everything on new laptop is working, will do a clean install of Big Sur on DAQ laptop.

Fern Pannell

  • MSci progress meeting with Jenny Thomas went very well!
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