Proton Calorimetry/Meetings/2020/07/01: Difference between revisions
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=== Present === | === Present === | ||
'''Simon Jolly''', '''Laurent Kelleter''', '''Saad Shaikh''', '''Raffaella Radogna''' | '''Simon Jolly''', '''Laurent Kelleter''', '''Saad Shaikh''', '''Raffaella Radogna''', '''Fern Pannell''' | ||
=== [[ELogs/RaffaellaRadogna|Raffaella Radogna]] === | === [[ELogs/RaffaellaRadogna|Raffaella Radogna]] === | ||
* Discussed with BEAMS fellowship opportunities | |||
* Implemented the geometry of the integrated QA detector in TOPAS to produce a nice figure for the fellowship proposal | |||
* Started powering up FPGA and learning VHDL | |||
* Will be connected with Simon on the 2nd July 15.30 to perform measurements for Laurents thesys | |||
* Will be off on Friday 3rd July | |||
* Will email Ruben about fellowsips | |||
=== [[ELogs/SaadShaikh|Saad Shaikh]] === | === [[ELogs/SaadShaikh|Saad Shaikh]] === | ||
*Seem to be making good progress on code for communicating FPGA with DDC232: developing from scratch in VHDL using DDC232 datasheet guidelines. | |||
**Currently debugging so that code compiles on Vivado. | |||
**Will need to develop a 'test bench' to test code in simulation before trying it out on hardware. | |||
**Need to debug UART interface project and figure out how to send data received from DDC232 to computer through UART. | |||
***UART is probably only fast enough to support integration time of about 750 us. Will need to investigate other methods of data retrieval down the line. | |||
=== [[ELogs/LaurentKelleter|Laurent Kelleter]] === | === [[ELogs/LaurentKelleter|Laurent Kelleter]] === | ||
* Discussed with Raffy and Simon the final list of measurements that Simon will take in 30' on July 2nd at 15.30 | |||
Latest revision as of 17:11, 8 July 2020
Minutes for UCL Proton Calorimetry Meetings, 1st July
Present
Simon Jolly, Laurent Kelleter, Saad Shaikh, Raffaella Radogna, Fern Pannell
Raffaella Radogna
- Discussed with BEAMS fellowship opportunities
- Implemented the geometry of the integrated QA detector in TOPAS to produce a nice figure for the fellowship proposal
- Started powering up FPGA and learning VHDL
- Will be connected with Simon on the 2nd July 15.30 to perform measurements for Laurents thesys
- Will be off on Friday 3rd July
- Will email Ruben about fellowsips
Saad Shaikh
- Seem to be making good progress on code for communicating FPGA with DDC232: developing from scratch in VHDL using DDC232 datasheet guidelines.
- Currently debugging so that code compiles on Vivado.
- Will need to develop a 'test bench' to test code in simulation before trying it out on hardware.
- Need to debug UART interface project and figure out how to send data received from DDC232 to computer through UART.
- UART is probably only fast enough to support integration time of about 750 us. Will need to investigate other methods of data retrieval down the line.
Laurent Kelleter
- Discussed with Raffy and Simon the final list of measurements that Simon will take in 30' on July 2nd at 15.30