Proton Calorimetry/Meetings/2021/05/12: Difference between revisions
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=== [[ELogs/SaadShaikh|Saad Shaikh]] === | === [[ELogs/SaadShaikh|Saad Shaikh]] === | ||
* | *Discussed with Marko aspects of design of next DDC232 board: FPGA-DDC232 connection, power supplies, etc. | ||
**Marko making good progress on daisy-chain issues. | |||
**Design of rev. C DDC232 board can start. | |||
**Will ask Matt/Erdem about dual-PMOD vs. FMC connection, and sending signals over (micro-)HDMI. | |||
*Finished analysis of UCLH test beam, uploaded results to [http://www.hep.ucl.ac.uk/pbt/wiki/Proton_Calorimetry/Experimental_Runs/2021/Apr15 experiment page]. | |||
*Added option to replay script to replay measurement with background subtraction and calibration. | |||
*Consolidating CMOS analysis code to work with both HIT and UCLH with minimal overhead. | |||
**Porting analysis routines from old Eclipse setup. | |||
*Updated [http://www.hep.ucl.ac.uk/pbt/wiki/Proton_Calorimetry/Detector_Analysis detector analysis page] with information on current photodiode analysis routines. | |||
*Will investigate reading from too many boards and compiling FPGA code with very large maximum number of DDC232 boards. | |||
Latest revision as of 13:57, 12 May 2021
Minutes for UCL Proton Calorimetry Meetings, 12th May
Present
Simon Jolly, Raffaella Radogna, Saad Shaikh
Saad Shaikh
- Discussed with Marko aspects of design of next DDC232 board: FPGA-DDC232 connection, power supplies, etc.
- Marko making good progress on daisy-chain issues.
- Design of rev. C DDC232 board can start.
- Will ask Matt/Erdem about dual-PMOD vs. FMC connection, and sending signals over (micro-)HDMI.
- Finished analysis of UCLH test beam, uploaded results to experiment page.
- Added option to replay script to replay measurement with background subtraction and calibration.
- Consolidating CMOS analysis code to work with both HIT and UCLH with minimal overhead.
- Porting analysis routines from old Eclipse setup.
- Updated detector analysis page with information on current photodiode analysis routines.
- Will investigate reading from too many boards and compiling FPGA code with very large maximum number of DDC232 boards.