Proton Calorimetry/Meetings/2020/11/04: Difference between revisions
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=== Present === | === Present === | ||
'''Simon Jolly''','''Raffaella Radogna''', '''Saad Shaikh''', '''Fern Pannell''' | '''Simon Jolly''', '''Raffaella Radogna''', '''Saad Shaikh''', '''Fern Pannell''' | ||
=== [[ELogs/RaffaellaRadogna|Raffaella Radogna]] === | === [[ELogs/RaffaellaRadogna|Raffaella Radogna]] === | ||
*Presented quickly preliminary results about PD output [http://www.hep.ucl.ac.uk/pbt/wikiData/presentations/2020/RR04112020_QuARC_FPGA_16PDs_results.pdf slides showing results] (updated version) | |||
=== [[ELogs/SaadShaikh|Saad Shaikh]] === | === [[ELogs/SaadShaikh|Saad Shaikh]] === | ||
Latest revision as of 15:33, 17 November 2020
Minutes for UCL Proton Calorimetry Meetings, 4th November
Present
Simon Jolly, Raffaella Radogna, Saad Shaikh, Fern Pannell
Raffaella Radogna
- Presented quickly preliminary results about PD output slides showing results (updated version)
Saad Shaikh
- Managed to run Nexys Video USB tutorial at around 50 Mb/s.
- Will start working on implementing USB interface in DDC232 FPGA design.
- Added functionality to send ASCII commands to set FSR remotely.
- Will investigate adding some functionality to set different integration times without reconfiguring FPGA.
- Results from LED tests at UCL show increasing fluctuation/noise with longer integration times and smaller FSR - unsure why this is the case. Also observe 0 values in channels, which should not be possible.
- Tested integration time of 2000us with 350pC FSR using ILA: confirmed that CONV remains in sync with CLK and could see many 0s being sent on DOUT under low light levels.
- Could be low light levels with LED.
- Will continue to test setup at UCL with Raffy.