Proton Calorimetry/Meetings/2020/06/03: Difference between revisions

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(Created page with "== Minutes for UCL Proton Calorimetry Meetings, 3rd June (Everyone is working from home) == === Present === '''Simon Jolly''','''Laurent Kelleter''', '''Saad Shaikh''', '''Raf...")
 
 
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=== [[ELogs/RaffaellaRadogna|Raffaella Radogna]] ===
=== [[ELogs/RaffaellaRadogna|Raffaella Radogna]] ===
 
*Analysed C Nov18 and He and C Apr19 data comparing the reconstructed Bragg curve with GSI DDDs [http://www.hep.ucl.ac.uk/pbt/wikiData/presentations/2020/RR03062020_QBplusTail_ComparisonWithGSI_DDD.pdf plots]
** Not possible to evaluate the goodness of the range reconstruction: GSI DDD energy steps are different from HIT, beam settings are also not clear (we don't know if a ripple filtre was used and the beam offset.)
** We will need HIT DDDs for proper comparison
* Will read ch9 and ch2 of Laurent;s thesis
* Will make a windows partition for FPGA programming
** will investigate with Tony ans Simon the available Win OS license
* First two prototypes of the customised front-end board arrived at CosyLab
** Marko tested the power supply and reference voltage
** one board will be shipped to Saad  and the other to Raffy
** Marko will prepare cable for connecting board to power supply and to the FPGA board PMOD.
** Marko will also configure resistors for stand-alone operation.


=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
 
*Finished reading and giving feedback on Laurent's thesis.
*Tested He and C fitting using GSI DDDs as reference.
**Can't say much about quality of fitting and Bragg curve reconstruction as GSI data uses a ripple filter and has different energy steps to HIT. Need to compare with actual HIT FLUKA simulation.
*Finished Udemy online course on FPGA programming.
**Some useful introductory exercises using basic I/O on Zybo board beyond "Hello World" Blinky exercise.
**Will move onto Xilinx University Programme material to continue training.
*Front-end boards have been made by CosyLab!
**Will analyse datasheet for TI DDC232 to understand I/O signals and present report on timeline for operation.
*Need to get serial interface working to send commands from computer to FPGA.
**Have downloaded Tera Term terminal emulator, will find example code to get it working.
**Need to buy USB-UART converter expansion module for Zybo Z7 to communicate with FPGA without having to go through on-board processor.
*Will start going through example Verilog code for DDC264EVM FPGA serial interface.


=== [[ELogs/LaurentKelleter|Laurent Kelleter]] ===
=== [[ELogs/LaurentKelleter|Laurent Kelleter]] ===

Latest revision as of 08:50, 17 June 2020

Minutes for UCL Proton Calorimetry Meetings, 3rd June (Everyone is working from home)

Present

Simon Jolly,Laurent Kelleter, Saad Shaikh, Raffaella radogna

Raffaella Radogna

  • Analysed C Nov18 and He and C Apr19 data comparing the reconstructed Bragg curve with GSI DDDs plots
    • Not possible to evaluate the goodness of the range reconstruction: GSI DDD energy steps are different from HIT, beam settings are also not clear (we don't know if a ripple filtre was used and the beam offset.)
    • We will need HIT DDDs for proper comparison
  • Will read ch9 and ch2 of Laurent;s thesis
  • Will make a windows partition for FPGA programming
    • will investigate with Tony ans Simon the available Win OS license
  • First two prototypes of the customised front-end board arrived at CosyLab
    • Marko tested the power supply and reference voltage
    • one board will be shipped to Saad and the other to Raffy
    • Marko will prepare cable for connecting board to power supply and to the FPGA board PMOD.
    • Marko will also configure resistors for stand-alone operation.

Saad Shaikh

  • Finished reading and giving feedback on Laurent's thesis.
  • Tested He and C fitting using GSI DDDs as reference.
    • Can't say much about quality of fitting and Bragg curve reconstruction as GSI data uses a ripple filter and has different energy steps to HIT. Need to compare with actual HIT FLUKA simulation.
  • Finished Udemy online course on FPGA programming.
    • Some useful introductory exercises using basic I/O on Zybo board beyond "Hello World" Blinky exercise.
    • Will move onto Xilinx University Programme material to continue training.
  • Front-end boards have been made by CosyLab!
    • Will analyse datasheet for TI DDC232 to understand I/O signals and present report on timeline for operation.
  • Need to get serial interface working to send commands from computer to FPGA.
    • Have downloaded Tera Term terminal emulator, will find example code to get it working.
    • Need to buy USB-UART converter expansion module for Zybo Z7 to communicate with FPGA without having to go through on-board processor.
  • Will start going through example Verilog code for DDC264EVM FPGA serial interface.

Laurent Kelleter

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