Proton Calorimetry/Meetings/2020/07/01 - Revision history

RaffaellaRadogna at 17:11, 8 July 2020

2020-07-08T17:11:22Z

← Older revision		Revision as of 17:11, 8 July 2020
Line 8:		Line 8:
	* Discussed with BEAMS fellowship opportunities		* Discussed with BEAMS fellowship opportunities
	* Implemented the geometry of the integrated QA detector in TOPAS to produce a nice figure for the fellowship proposal		* Implemented the geometry of the integrated QA detector in TOPAS to produce a nice figure for the fellowship proposal
			* Started powering up FPGA and learning VHDL
			* Will be connected with Simon on the 2nd July 15.30 to perform measurements for Laurents thesys
			* Will be off on Friday 3rd July
			* Will email Ruben about fellowsips

	=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===		=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===

RaffaellaRadogna at 13:30, 8 July 2020

2020-07-08T13:30:59Z

← Older revision		Revision as of 13:30, 8 July 2020
Line 6:		Line 6:

	=== [[ELogs/RaffaellaRadogna\|Raffaella Radogna]] ===		=== [[ELogs/RaffaellaRadogna\|Raffaella Radogna]] ===
	*		* Discussed with BEAMS fellowship opportunities
			* Implemented the geometry of the integrated QA detector in TOPAS to produce a nice figure for the fellowship proposal

	=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===		=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===

RaffaellaRadogna at 13:29, 8 July 2020

2020-07-08T13:29:00Z

← Older revision		Revision as of 13:29, 8 July 2020
Line 6:		Line 6:

	=== [[ELogs/RaffaellaRadogna\|Raffaella Radogna]] ===		=== [[ELogs/RaffaellaRadogna\|Raffaella Radogna]] ===
			*

	=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===		=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===
Line 16:		Line 16:

	=== [[ELogs/LaurentKelleter\|Laurent Kelleter]] ===		=== [[ELogs/LaurentKelleter\|Laurent Kelleter]] ===
			* Discussed with Raffy and Simon the final list of measurements that Simon will take in 30' on July 2nd at 15.30

SaadShaikh: /* Saad Shaikh */

2020-07-01T14:18:18Z

Saad Shaikh

← Older revision		Revision as of 14:18, 1 July 2020
Line 9:		Line 9:

	=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===		=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===
	*~~Making~~ good progress on code for communicating FPGA with DDC232: developing from scratch in VHDL using DDC232 datasheet guidelines.		*Seem to be making good progress on code for communicating FPGA with DDC232: developing from scratch in VHDL using DDC232 datasheet guidelines.
	**Currently debugging so that code compiles on Vivado.		**Currently debugging so that code compiles on Vivado.
	**Will need to develop a 'test bench' to test code in simulation before trying it out on hardware.		**Will need to develop a 'test bench' to test code in simulation before trying it out on hardware.
	**Need to debug UART interface ~~code~~ and figure out how to send data received from DDC232 to computer through UART.		**Need to debug UART interface project and figure out how to send data received from DDC232 to computer through UART.
	***UART is probably only fast enough to support integration time of about 750 us. Will need to investigate other methods of data retrieval down the line.		***UART is probably only fast enough to support integration time of about 750 us. Will need to investigate other methods of data retrieval down the line.

	=== [[ELogs/LaurentKelleter\|Laurent Kelleter]] ===		=== [[ELogs/LaurentKelleter\|Laurent Kelleter]] ===

SaadShaikh: /* Saad Shaikh */

2020-07-01T14:17:13Z

Saad Shaikh

← Older revision		Revision as of 14:17, 1 July 2020
Line 9:		Line 9:

	=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===		=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===
	*Making good progress on code for communicating FPGA with DDC232: ~~developed~~ from scratch in VHDL using DDC232 datasheet guidelines.		*Making good progress on code for communicating FPGA with DDC232: developing from scratch in VHDL using DDC232 datasheet guidelines.
	**Currently debugging so that code compiles on Vivado.		**Currently debugging so that code compiles on Vivado.
	**Will need to develop a 'test bench' to test code in simulation before trying it out on hardware.		**Will need to develop a 'test bench' to test code in simulation before trying it out on hardware.

SaadShaikh: /* Saad Shaikh */

2020-07-01T14:16:51Z

Saad Shaikh

← Older revision		Revision as of 14:16, 1 July 2020
Line 9:		Line 9:

	=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===		=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===
	*Making good progress on code for communicating FPGA with DDC232.		*Making good progress on code for communicating FPGA with DDC232: developed from scratch in VHDL using DDC232 datasheet guidelines.
	**Currently debugging so that code compiles on Vivado.		**Currently debugging so that code compiles on Vivado.
	**Will need to develop a 'test bench' to test code in simulation before trying it out ~~in real life~~.		**Will need to develop a 'test bench' to test code in simulation before trying it out on hardware.
	**Need to debug UART interface code and figure out how to send data received from DDC232 to computer through UART.		**Need to debug UART interface code and figure out how to send data received from DDC232 to computer through UART.
	***UART is probably only fast enough to support integration time of about 750 us. Will need to investigate other methods of data retrieval.		***UART is probably only fast enough to support integration time of about 750 us. Will need to investigate other methods of data retrieval down the line.

	=== [[ELogs/LaurentKelleter\|Laurent Kelleter]] ===		=== [[ELogs/LaurentKelleter\|Laurent Kelleter]] ===

SaadShaikh: /* Minutes for UCL Proton Calorimetry Meetings, 1st July */

2020-07-01T14:15:20Z

Minutes for UCL Proton Calorimetry Meetings, 1st July

← Older revision		Revision as of 14:15, 1 July 2020
Line 3:		Line 3:
	=== Present ===		=== Present ===

	'''Simon Jolly''', '''Laurent Kelleter''', '''Saad Shaikh''', '''Raffaella Radogna'''		'''Simon Jolly''', '''Laurent Kelleter''', '''Saad Shaikh''', '''Raffaella Radogna''', '''Fern Pannell'''

	=== [[ELogs/RaffaellaRadogna\|Raffaella Radogna]] ===		=== [[ELogs/RaffaellaRadogna\|Raffaella Radogna]] ===
Line 9:		Line 9:

	=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===		=== [[ELogs/SaadShaikh\|Saad Shaikh]] ===
			*Making good progress on code for communicating FPGA with DDC232.
			**Currently debugging so that code compiles on Vivado.
			**Will need to develop a 'test bench' to test code in simulation before trying it out in real life.
			**Need to debug UART interface code and figure out how to send data received from DDC232 to computer through UART.
			***UART is probably only fast enough to support integration time of about 750 us. Will need to investigate other methods of data retrieval.

	=== [[ELogs/LaurentKelleter\|Laurent Kelleter]] ===		=== [[ELogs/LaurentKelleter\|Laurent Kelleter]] ===

RaffaellaRadogna: Created page with "== Minutes for UCL Proton Calorimetry Meetings, 1st July == === Present === '''Simon Jolly''', '''Laurent Kelleter''', '''Saad Shaikh''', '''Raffaella Radogna''' === [[ELogs/R..."

2020-07-01T12:57:46Z

Created page with "== Minutes for UCL Proton Calorimetry Meetings, 1st July == === Present === '''Simon Jolly''', '''Laurent Kelleter''', '''Saad Shaikh''', '''Raffaella Radogna''' === [[ELogs/R..."

New page

== Minutes for UCL Proton Calorimetry Meetings, 1st July ==

=== Present ===

'''Simon Jolly''', '''Laurent Kelleter''', '''Saad Shaikh''', '''Raffaella Radogna'''

=== [[ELogs/RaffaellaRadogna|Raffaella Radogna]] ===

=== [[ELogs/SaadShaikh|Saad Shaikh]] ===

=== [[ELogs/LaurentKelleter|Laurent Kelleter]] ===