Proton Calorimetry/Meetings/2019/10/04 - Revision history

RaffaellaRadogna: /* QuARC Task List */

2019-11-12T15:18:14Z

QuARC Task List

← Older revision		Revision as of 15:18, 12 November 2019
Line 27:		Line 27:
	## replacement for AIB		## replacement for AIB
	## speak to Bernard Bristoll (b.bristoll@ucl.ac.uk)		## speak to Bernard Bristoll (b.bristoll@ucl.ac.uk)
	## contact TI ~~and~~ to check if we can use AIB for our purposes (dedline Dec.)		## contact TI to check if we can use AIB for our purposes (dedline Dec.)
	## ask TI if we can use our customised AIB with the EVM		## ask TI if we can use our customised AIB with the EVM
	## speak to electrical eng. for circuit board DDC232 (about 10cm stacks considering 3mm layers)		## speak to electrical eng. for circuit board DDC232 (about 10cm stacks considering 3mm layers)

RaffaellaRadogna: /* QuARC Task List */

2019-10-08T11:00:14Z

QuARC Task List

← Older revision		Revision as of 11:00, 8 October 2019
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	# Front end (photodiode) electronics		# Front end (photodiode) electronics
	## replacement for AIB		## replacement for AIB
	## speak to Bernard ~~Bristol~~		## speak to Bernard Bristoll (b.bristoll@ucl.ac.uk)
	## contact TI and to check if we can use AIB for our purposes (dedline Dec.)		## contact TI and to check if we can use AIB for our purposes (dedline Dec.)
	## ask TI if we can use our customised AIB with the EVM		## ask TI if we can use our customised AIB with the EVM

RaffaellaRadogna: /* Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL) */

2019-10-04T16:28:20Z

Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL)

← Older revision		Revision as of 16:28, 4 October 2019
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	## FPGA that generates DDC232 signal (fake signal) trigger signal, each channel integrates for 200 ns, output from each channel		## FPGA that generates DDC232 signal (fake signal) trigger signal, each channel integrates for 200 ns, output from each channel
	## test signal into the FPGA board (test fake signal from the previous point). has to behave as interfacing with the real input (trigger that says to read out and a clock that integrates each channel).		## test signal into the FPGA board (test fake signal from the previous point). has to behave as interfacing with the real input (trigger that says to read out and a clock that integrates each channel).
			## buffer data to work at 5kHz
			## COMMS to PC (interface with FPGA)

	# Data analysis		# Data analysis
			## standalone version of the current analysis without ROOT
			## FPGA analysis (using ROOT libraries?)
			## GUI

RaffaellaRadogna: /* Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL) */

2019-10-04T16:10:10Z

Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL)

← Older revision		Revision as of 16:10, 4 October 2019
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	## ask TI if we can use our customised AIB with the EVM		## ask TI if we can use our customised AIB with the EVM
	## speak to electrical eng. for circuit board DDC232 (about 10cm stacks considering 3mm layers)		## speak to electrical eng. for circuit board DDC232 (about 10cm stacks considering 3mm layers)
			## manufacturing of 2 circuit boards: PD to SMA to board, permanent PD coupling to board
			## stable coupling of PD and SMA
			## mounting the circuit board in an enclosure

	# Back end (FPGA/comms) electronics		# Back end (FPGA/comms) electronics
			## buy FPGA prototyping board
			## FPGA that generates DDC232 signal (fake signal) trigger signal, each channel integrates for 200 ns, output from each channel
			## test signal into the FPGA board (test fake signal from the previous point). has to behave as interfacing with the real input (trigger that says to read out and a clock that integrates each channel).


	# Data analysis		# Data analysis

RaffaellaRadogna: /* Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL) */

2019-10-04T15:49:26Z

Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL)

@@ Line 15: / Line 15: @@
 # Scintillator manufacture
 # Photodiode coupling
 # Front end (photodiode) electronics
 # Back end (FPGA/comms) electronics
 # Data analysis

SimonJolly at 15:37, 4 October 2019

2019-10-04T15:37:02Z

← Older revision		Revision as of 15:37, 4 October 2019
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	'''Simon Jolly''', '''Laurent Kelleter''', '''Raffaella Radogna''', '''Saad Shaikh'''		'''Simon Jolly''', '''Laurent Kelleter''', '''Raffaella Radogna''', '''Saad Shaikh'''

			=== Current Status ===

			* '''RR''' presented current status.
			* Various photodiodes already purchased; DDC1128 EVM's purchased.
			** Simple light injection setup with 270nm LED.
			** EVM connected to photodiodes through removal of resistors on daughter board.

	=== QuARC Task List ===		=== QuARC Task List ===

			# Scintillator manufacture
			# Photodiode coupling
			# Front end (photodiode) electronics
			# Back end (FPGA/comms) electronics
			# Data analysis

SimonJolly: Created page with "== Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL) == === Present === '''Simon Jolly''', '''Laurent Kelleter''', '''Raffaella Rado..."

2019-10-04T14:47:02Z

Created page with "== Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL) == === Present === '''Simon Jolly''', '''Laurent Kelleter''', '''Raffaella Rado..."

New page

== Minutes for UCL Proton Calorimetry Meetings, 4th October 2019 (D17, Physics & Astronomy, UCL) ==

=== Present ===

'''Simon Jolly''', '''Laurent Kelleter''', '''Raffaella Radogna''', '''Saad Shaikh'''

=== QuARC Task List ===